The present invention relates to a method of driving a sustaining pulse for a plasma display panel and a driver circuit for driving a plasma display panel, and more particularly to a method of driving a sustaining pulse for a plasma display panel to keep sustaining discharges in stable intensity for each display cell independently from variation in load to the display cells as well as a driver circuit for driving a plasma display panel to keep sustaining discharges in stable intensity for each display cell independently from variation in load to the display cells.
The plasma display panel is advantageous in possible reduction in thickness thereof, and also in its large contrast in display without substantial flicker as well as advantageous in possible enlargement of its screen The plasma display panel is further advantageous in high response speed and realizing a multi-color display by utilizing a fluorescent material due to self-emission type display. In recent years, the plasma display panel has been becoming to be used widely in various fields of displays for computers and color-displays.
FIG. 1 is a circuit diagram illustrative of a conventional circuit configuration of a driver circuit for driving a display cell of a plasma display panel. The driver circuit is connected to a display cell 16. The driver circuit for driving the display cell 16 comprises an address driver 20, a scanning driver 21xe2x80x2 and a sustaining driver 22xe2x80x2. The address driver 20 is connected through a data electrode 7 to the display cell 16. The scanning driver 21xe2x80x2 is also connected through a scanning electrode 3 to the display cell 16. The sustaining driver 22xe2x80x2 is also connected through a sustaining electrode 4 to the display cell 16. The display cell 16 has a panel static capacitance between the scanning electrode 3 and the sustaining electrode 4. The address driver 20 comprises a complementary MOS circuit which comprises a series connection of an n-channel MOS field effect transistor T11 and a p-channel MOS field effect transistor T10 between a ground line and a high voltage line Vd, wherein the high voltage line is connected to the p-channel MOS field effect transistor T10, whilst the ground line is connected to the n-channel MOS field effect transistor T11. The data electrode 7 is connected to an intermediate point between the p-channel MOS field effect transistor T10 and the n-channel MOS field effect transistor T11.
The scanning driver 21xe2x80x2 comprises seven diodes D20, D21, D23, D31, D42, D52 and D54 and five n-channel MOS field effect transistors T21, T22, T23, T31 and T42 as well as two p-channel MOS field effect transistors T20 and T52. The scanning electrode 3 is connected to a first node N1 of the scanning driver 21xe2x80x2. The p-channel MOS field effect transistor T20 is connected in series between the first node N1 and a second node N2. The n-channel MOS field effect transistor T21 is connected in series between the first node N1 and a third node N3. The p-channel MOS field effect transistor T20 and the n-channel MOS field effect transistor T21 are connected in series between the second node N2 and the third node N3, and the first node as the intermediate point between the p-channel MOS field effect transistor T20 and the n-channel MOS field effect transistor T21 is connected to the scanning electrode 3. Two diodes D20 and D21 are connected in series between the second node N2 and the third node N3 in parallel to the series connection of the p-channel MOS field effect transistor T20 and the n-channel MOS field effect transistor T21. The diode D20 is connected between the first node N1 and the second node N2 in such a direction that the diode D20 allows a current from the first node N1 to the second node N2. The diode D21 is connected between the first node N1 and the third node N3 in such a direction that the diode D21 allows a current from the third node N3 to the first node N1. The second node N2 is connected to the sustaining driver 22xe2x80x2. The third node N3 is also connected to the sustaining driver 22xe2x80x2. The diode D23 and the n-channel MOS field effect transistor T23 are connected in series between the second node N2 and a voltage line Vbw which is applied with a voltage level Vbw. The diode D23 is connected between the second node N2 and the n-channel MOS field effect transistor T23 in such a direction that the diode D23 allows a current from the second node N2 to the n-channel MOS field effect transistor 723. The n-channel MOS field effect transistor T23 connected between the diode D23 and the voltage line Vbw. The diode D31 and the n-channel MOS field effect transistor T31 are connected in series between the second node N2 and a voltage line Vpe which is applied with a voltage level Vpe. The diode D31 is connected between the second node N2 and the n-channel MOS field effect transistor T31 in such a direction that the diode D31 allows a current from the second node N2 to the n-channel MOS field effect transistor T31. The n-channel MOS field effect transistor T31 connected between the diode D31 and the voltage line Vpe. The diode D42 and the n-channel MOS field effect transistor T42 are connected in series between the second node N2 and a voltage line Vs which is applied with a voltage level Vs. The diode D42 is connected between the second node N2 and the n-channel MOS field effect transistor T42 in such a direction that the diode D42 allows a current from the second node N2 to the n-channel MOS field effect transistor T42. The n-channel MOS field effect transistor T42 connected between the diode D42 and the voltage line Vs. The diode D54 and the n-channel MOS field effect transistor T22 are connected in series between the third node N3 and a voltage line Vw which is applied with a voltage level Vw. The diode D54 is connected between the third node N3 and the n-channel MOS field effect transistor T22 in such a direction that the diode D54 allows a current from the third node N3 to the n-channel MOS field effect transistor T22. The n-channel MOS field effect transistor T22 connected between the diode D54 and the voltage line Vw. The diode D52 and the p-channel MOS field effect transistor T52 are connected in series between the third node N3 and a ground line which is applied with a ground voltage level. The diode D52 is connected between the third node N3 and the p-channel MOS field effect transistor T52 in such a direction that the diode D52 allows a current from the p-channel MOS field effect transistor T52 to the third node N3. The p-channel MOS field effect transistor T52 connected between the diode D52 and the ground line.
The sustaining driver 22xe2x80x2 also comprises five diodes D30, D40, D50, D60 and D61 and four n-channel MOS field effect transistors T30 and T32, T60 and T61 as well as a single p-channel MOS field effect transistor T50. A fourth node N4 is connected to the sustaining electrode 4. The diode D30 and the n-channel MOS field effect transistor T30 are connected in series between the fourth node N4 and a voltage line Vp which is applied with a voltage level Vp. The diode D30 is connected between the fourth node N4 and the n-channel MOS field effect transistor T30 in such a direction that the diode D30 allows a current from the fourth node N4 to the n-channel MOS field effect transistor T30. The n-channel MOS field effect transistor T30 connected between the diode D30 and the voltage line Vp. The diode D40 and the n-channel MOS field effect transistor T32 arc connected in series between the fourth node N4 and a voltage line Vs which is applied with a voltage level Vs. The diode D40 is connected between the fourth node N4 and the n-channel MOS field effect transistor T32 in such a direction that the diode D40 allows a current from the fourth node N4 to the n-channel MOS field effect transistor T32. The n-channel MOS field effect transistor T32 connected between the diode D40 and the voltage line Vs. The diode D50 and the p-channel MOS field effect transistor T50 are connected in series between the fourth node N4 and a ground line which is applied with a ground potential. The diode D50 is connected between the fourth node N4 and the p-channel MOS field effect transistor T50 in such a direction that the diode D50 allows a current from the p-channel MOS field effect transistor T50 to the fourth node N4. The p-channel MOS field effect transistor T50 connected between the diode D50 and the ground line. The fourth node N4 is also connected through a reactance L60 to a fifth node N5. The diode D60 and the n-channel MOS field effect transistor T60 are connected in series between the fifth node N5 and the third node N3 of the scanning driver 21xe2x80x2. The diode D60 is connected between the third node N3 and the n-channel MOS field effect transistor T60 in such a direction that the diode D60 allows a current from the n-channel MOS field effect transistor T60 to the third node N3. The n-channel MOS field effect transistor T60 connected between the diode D60 and the fifth node N5. The diode D61 and the n-channel MOS field effect transistor T61 are also connected in series between the fifth node N5 and the second node N2 of the scanning driver 21xe2x80x2. The diode D61 is connected between the second node N2 and the n-channel MOS field effect transistor T61 in such a direction that the diode D61 allows a current from the second node N2 to the n-channel MOS field effect transistor T61. The n-channel MOS field effect transistor T61 connected between the diode D61 and the fifth node N5.
The above circuit operates as follows. In a preliminary discharge time period, the n-channel MOS field effect transistor T30 turns ON, so that the diode D30 causes the fourth node N4 and the sustaining electrode 4 to have the voltage level Vp, whereby a preliminary discharge pulse Pp is applied to the sustaining electrode 4. Concurrently, the p-channel MOS field effect transistor T52 is placed in the ON state, so that the series connection of the diodes D52 and D21 keeps the scanning electrode 3 in the ground potential.
Thereafter, the n-channel MOS field effect transistor T31 turns ON, so that series connection of the diodes D31 and D20 causes the second node N2 and the scanning electrode 3 to have the voltage level Vpe, whereby a preliminary discharge erasing pulse Ppe is applied to the scanning electrode 3. Concurrently, the p-channel MOS field effect transistor T50 is placed in the ON state, so that the diode D50 causes the sustaining electrode 4 to have the ground potential.
During the above preliminary discharge time period, the p-channel MOS field effect transistor T10 remains OFF state whilst the n-channel MOS field effect transistor T11 remains ON state, so that the data electrode 7 remains to have the ground level.
In a writing discharge time period, the n-channel MOS field effect transistor T23 turns ON, so that series connection of the diodes D23 and D20 causes the second node N2 and the scanning electrode 3 to have the voltage level Vbw. Concurrently, the p-channel MOS field effect transistor T50 is placed in the ON state, so that the diode D50 causes the sustaining electrode 4 to have the ground potential. Further, the n-channel MOS field effect transistor T22 is placed in the ON state. In these states, the n-channel MOS field effect transistor T21 is selectively switched into the ON state, so that the potential of the first node N1 and the scanning electrode 3 is dropped to the voltage level Vw, whereby the scanning pulse Pw is applied to the scanning electrode 3. For carrying out the writing discharge, in response to this scanning pulse Pw, the p-channel MOS field effect transistor T10 turns ON whilst the n-channel MOS field effect transistor T11 turns OFF, so that the data electrode 7 becomes to have the voltage level Vd, whereby the data pulse is applied to the data electrode 7.
A sustaining pulse may be obtained by various methods, for example, a power recovery method disclosed in Japanese Patent Publication No. 2755201 as mentioned below. The following operations are to apply a negative potential sustaining pulse to the sustaining electrode 4. The n-channel MOS field effect transistor T61 turns ON, so that charges accumulated in the panel static capacitance Cp are caused to flow through the scanning electrode 3, the diodes D20 and D61 and further through the n-channel MOS field effect transistor T61 and the reactance L60 to the fourth node N4 and the sustaining electrode 4, whereby a resonance phenomenon is caused to charge opposite-polarity charges to the panel capacitance Cp. As a result, the scanning electrode 3 is made into the potential G0 and the sustaining electrode 4 is made into the potential Vs0.
Thereafter, in order to supply the sustaining discharge current, the n-channel MOS field effect transistor T32 turns ON, so that the potential of the fourth node N4 and the sustaining electrode 4 is dropped into the voltage level Vs. Concurrently, the p-channel MOS field effect transistor T52 turns ON, so that the potential of the first node N1 and the scanning electrode 3 is risen up to the ground level GND.
The following operations are to apply a negative potential scanning pulse to the scanning electrode 3. The n-channel MOS field effect transistor T60 turns ON, so that charges accumulated in the panel static capacitance Cp are caused to flow through the sustaining electrode 4, the fourth node N4, the reactance L60 and further through the n-channel MOS field effect transistor T60 and the diodes D60 and D21 to the scanning electrode 3, whereby a resonance phenomenon is caused to charge opposite-polarity charges to the panel capacitance Cp. As a result, the sustaining electrode 4 is made into the potential G0 and the scanning electrode 3 is made into the potential Vs0.
Thereafter, in order to supply the sustaining discharge current, the n-channel MOS field effect transistor T42 turns ON, so that the potential of the first node N1 and the scanning electrode 3 is dropped to the voltage level Vs. Concurrently, the p-channel MOS field effect transistor T50 turns ON, so that the potential of the fourth node N4 and the sustaining electrode 4 is risen to the ground level GND.
The above operations are repeated to alternate the potential levels of the scanning electrode 3 and the sustaining electrode 4, thereby carrying out the required sustaining discharge. For the plasma display, it is easy to select light-ON or OFF, however difficult to adjust analogically the brightness. If the images are required to be displayed in multi-grayscale, then a sub-field method is utilized. The display cells on the plasma display show luminescence upon application of the sustaining pulse under the condition that the charges are written or charged to the capacitance. In the sub-field method, the brightness of the display cell is considered to be integral effects of integrating the visibility, and the number of applications of the sustaining pulse is adjusted to adjust the brightness of the display cell. One frame as a main frame of the display screen is divided into plural sub-fields where intervals for applying sustaining pulses as the driving pulses are different depending upon individual sub-fields. For example, image signals comprise 6 bits binary scales to display an image in 64 grayscales. FIG. 2 is a diagram illustrative of timings of applications of sustaining pulses for individual sub-fields SF1, SF2, SF3, SF4, SF5 and SF6 in one frame. The one frame is divided into six sub-fields SF1, SP2, SF3, SF4, SF5 and SF6. In the first sub-field SF1, after the preliminary discharge time period and the writing discharge time period, a first sustaining discharge time period exists which corresponds to one time application of the sustaining pulse. In the second sub-field SF2 following to the first sub-field SF1, after the same preliminary discharge time period and the same writing discharge time period as those in the first sub-field SF1, a second sustaining discharge time period exists which corresponds to two times application of the sustaining pulse. In the third sub-field SF3 following to the second sub-field SP2, after the same preliminary discharge time period and the same writing discharge time period as those in the second sub-field SF2, a third sustaining discharge time period exists which corresponds to four times application of the sustaining pulse. In the fourth sub-field SF4 following to the third sub-field SF3, after the same preliminary discharge time period and the same writing discharge time period as those in the third sub-field SF3, a fourth sustaining discharge time period exists which corresponds to eight times application of the sustaining pulse. In the fifth sub-field SF5 following to the fourth sub-field SF4, after the same preliminary discharge time period and the same writing discharge time period as those in the fourth sub-field SF4, a fifth sustaining discharge time period exists which corresponds to sixteen times application of the sustaining pulse In the sixth sub-field SF6 following to the fifth sub-field SF5, after the same preliminary discharge time period and the same writing discharge time period as those in the fifth sub-field SF5, a sixth sustaining discharge time period exists which corresponds to thirty two times application of the sustaining pulse. Those various sustaining pulse sub-field application time periods are optionally alone or in combination so that 64 different sustaining pulse one frame application time periods may be obtained, for which reason it is possible to realize the 64 gray-scales display corresponding to the number of the applications of the sustaining pulse in the one frame, so that the brightness corresponding to the 64 gray-scales corresponding to 64 different sustaining pulse application time periods are obtained.
The above conventional technique has the following problems. If the number of the luminescent cells are changed whereby a display load is changed in the sustaining discharge time period, variations in the sustaining discharge current to be supplied to the individual display cells is caused by resistances of the scanning electrode 3 and the sustaining electrode 4 and also by output impedance of the sustaining discharge current supply circuit, for which reason even the number of the pulses is the same for the display cells, the brightness is different between the display cells. If the display load of each sub-field is varied, then the 64 brightness levels are not uniformly varied, whereby adjacent two upper and lower brightness levels are inverted so that an upper brightness level, which should have to be upper than an adjacent lower brightness level, may actually be lower than the adjacent lower brightness level. It is no longer possible to obtain correct image display, resulting in a remarkable deterioration in image quality. Even if the adjacent two upper and lower brightness levels are not inverted, then it is no longer possible to obtain accurate grayscales whereby the display quality is poor.
FIG. 3A is a diagram illustrative of waveforms sustaining pulse and sustaining discharge current for each display cell in the prior art, where a display load is small. FIG. 3B is a diagram illustrative of waveforms sustaining pulse and sustaining discharge current for each display cell in the prior art, where a display load is large. If the display load is small, then a distortion of the sustaining pulse waveform is also small and a peak value of the sustaining discharge current is large. If, however, the display load is large, then a distortion of the sustaining pulse waveform is also large and a peak value of the sustaining discharge current is small. Further, the peak value of the discharge current is almost proportional to the brightness, for which reason if the display load is small, then the brightness is increased. If, however, the display load is large, then the brightness is decreased.
In the above circumstances, it had been required to develop a novel driver circuit for driving a sustaining pulse for a plasma display panel and a novel method of driving a sustaining pulse for the plasma display panel free from the above problem.
Accordingly, it is an object of the present invention to provide a novel driver circuit for driving a sustaining pulse for a plasma display panel free from the above problems.
It is a further object of the present invention to provide a novel driver circuit for driving a sustaining pulse for a plasma display panel, which is capable of keeping the stability of intensity of the sustaining discharge current for each display cell independently from variation of the display load.
It is a still further object of the present invention to provide a novel method of driving a sustaining pulse for a plasma display panel free from the above problems.
It is yet a further object of the present invention to provide a novel method of driving a sustaining pulse for a plasma display panel, which is capable of keeping the stability of intensity of the sustaining discharge current for each display cell independently from variation of the display load.
The first present invention provides a method of driving a sustaining pulse for a plasma display panel, wherein sustaining pulses are generated, which comprise plural sustaining discharge current supply pulses having different achieving voltage levels from each other and slope pulses, so that, after the slope pulses are generated and outputted, the sustaining discharge current supply pulses having the different achieving voltage levels are applied in sequence of a magnitude of difference between the different achieving voltage levels and a potential of a final one of the sustaining discharge current supply pulses.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.